/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/**
 * @file  desc.h
 * @brief Semidrive. AUTOSAR 4.3.1 MCAL Eth plugins.
 */

#ifndef DESCS_H
#define DESCS_H

#ifdef __cplusplus
extern "C" {
#endif

#include "Part.h"
#include "RegHelper.h"
#include "dwmac_common.h"

/* DES3 Common Descriptor */
#define DES3_LAST_DESCRIPTOR            BIT(28)
#define DES3_LAST_DESCRIPTOR_SHIFT      28u
#define DES3_FIRST_DESCRIPTOR           BIT(29)
#define DES3_CONTEXT_TYPE               BIT(30)
#define DES3_CONTEXT_TYPE_SHIFT         30u
#define DES3_OWN                        BIT(31)
#define DES3_OWN_SHIFT                  31u

/* TDES2 Normal Descriptor (Read Format) */
#define TDES2_BUFFER1_LEN_MASK          GENMASK(13, 0)
#define TDES2_VLAN_PROC_MASK            GENMASK(15, 14)
#define TDES2_VLAN_PROC_MASK_SHIFT      14u
#define TDES2_BUFFER2_LEN_MASK          GENMASK(29, 16)
#define TDES2_BUFFER2_LEN_MASK_SHIFT    16u
#define TDES2_TTSP_WMWD                 BIT(30)
#define TDES2_INT_ON_COMP               BIT(31)

/* TDES3 Normal Descriptor (Read Format) */
#define TDES3_FRAME_LEN_MASK            GENMASK(14, 0)
#define TDES3_CKSUM_INS_DISABLE         (0)
#define TDES3_CKSUM_INS_L3              BIT(16)
#define TDES3_CKSUM_INS_L3L4_WITHOUT_PH BIT(17)
#define TDES3_CKSUM_INS_L3L4_WITH_PH    (BIT(16) | BIT(17))
#define TDES3_CKSUM_INS_MASK            GENMASK(17, 16)
#define TDES3_CKSUM_INS_SHIFT           16u
#define TDES3_TCP_PAYLOAD_LEN_MASK      GENMASK(17, 0)
#define TDES3_TCP_SEG_ENABLE            BIT(18)
#define TDES3_TCP_HEAD_LEN_SHIFT        19u
#define TDES3_SLOT_NUM_CTRL_MASK        GENMASK(22, 19)
#define TDES3_SA_INSERTION_CTRL_MASK    GENMASK(25, 23)
#define TDES3_CRC_PAD_CTRL_MASK         GENMASK(27, 26)
#define TDES3_OWN                       BIT(31)

/* TDES3 Normal Descriptor (Write-Back Format) */
#define TDES3_IP_HDR_ERR                BIT(0)
#define TDES3_DEFERRED                  BIT(1)
#define TDES3_UNDERFLOW_ERR             BIT(2)
#define TDES3_EXC_DEFERRAL              BIT(3)
#define TDES3_COLL_CNT_MASK             GENMASK(7, 4)
#define TDES3_COLL_CNT_SHIFT            4u
#define TDES3_EXC_COLL                  BIT(8)
#define TDES3_LATE_COLL                 BIT(9)
#define TDES3_NO_CARRIER                BIT(10)
#define TDES3_LOSS_OF_CARRIER           BIT(11)
#define TDES3_PAYLOAD_ERR               BIT(12)
#define TDES3_PKT_FLUSHED               BIT(13)
#define TDES3_JABBER_TIMEOUT            BIT(14)
#define TDES3_ERR_SUMMARY               BIT(15)
#define TDES3_TS_STATUS                 BIT(17)
#define TDES3_TS_STATUS_SHIFT           17u

/* TDES3 Context Descriptor */
#define TDES3_CTXT_TCMSSV               BIT(26)

/* RDES0 Normal Descriptor (Write-Back Format) */
#define RDES0_OUTER_VLAN_TAG_MASK       GENMASK(15, 0)

/* RDES1 Normal Descriptor (Write-Back Format) */
#define RDES1_PTP_PKT_TYPE              BIT(12)
#define RDES1_PTP_VERSION               BIT(13)
#define RDES1_TS_AVAIL                  BIT(14)
#define RDES1_TS_AVAIL_SHIFT            14u

/* RDES3 Normal Descriptor (Write-Back Format) */
#define RDES3_PACKET_LEN_MASK           GENMASK(14, 0)
#define RDES3_ERR_SUMMARY               BIT(15)
#define RDES3_RS1V                      BIT(26)
#define DES3_LAST_DESCRIPTOR            BIT(28)
#define DES3_FIRST_DESCRIPTOR           BIT(29)

/* RDES3 Normal Descriptor (Read Format) */
#define RDES3_BUFFER1_ADDR_VALID        BIT(24)
#define RDES3_INT_EN_ON_COMPLETION      BIT(30)
#define RDES3_OWN                       BIT(31)

/* Basic descriptor structure for normal and alternate descriptors */

#define ETH_DESC_ALIGN CACHE_LINE

struct dma_desc {
    uint32 des0;
    uint32 des1;
    uint32 des2;
    uint32 des3;
    uint32 des4;
    uint32 des5;
    uint32 des6;
    uint32 des7;
#if (ETH_CACHEABLE_NEEDED == STD_ON)
    uint32 pad[(ETH_DESC_ALIGN - 32) / 4];
} __attribute__((aligned(ETH_DESC_ALIGN)));
#else
};
#endif

/* Transmit checksum insertion control */
#define TX_CIC_FULL 3u   /* Include IP header and pseudoheader */


/* source address replace enable without source addr */
#define TX_SAIC_REPLACE 2u
#define TDES3_TX_SAIC_REPLACE_SAIFT 23u


#define TDES3_SA_REPLACE_DESCRIPTOR (TDES3_SA_INSERTION_CTRL_MASK & \
        (TX_SAIC_REPLACE << TDES3_TX_SAIC_REPLACE_SAIFT));

/* crc and pad insert automaticaly by mac */
#define TX_CPC_CRC_PAD_INSER    0u
/* only crc  insert automaticaly by mac */
#define TX_CPC_CRC_INSER    1u
/* only pad  insert automaticaly by mac */
#define TX_CPC_PAD_INSER    2u
/* crc and pad insert by software, mac only repace crc*/
#define TX_CPC_CRC_REPLACE  3u

#define TDES3_TX_CPC_REPLACE_SAIFT  26u


#define TDES3_CRC_PAD_INSER_DESCRIPTOR \
(TX_CPC_CRC_PAD_INSER<<TDES3_TX_CPC_REPLACE_SAIFT)
#define TDES3_CRC_INSER_DESCRIPTOR \
(TX_CPC_CRC_INSER<<TDES3_TX_CPC_REPLACE_SAIFT)
#define TDES3_PAD_INSER_DESCRIPTOR \
(TX_CPC_PAD_INSER<<TDES3_TX_CPC_REPLACE_SAIFT)
#define TDES3_CRC_REPLACE_DESCRIPTOR \
(TX_CPC_CRC_REPLACE<<TDES3_TX_CPC_REPLACE_SAIFT)




#define DESC_FLAGS_TX_FIRST     BIT(0)
#define DESC_FLAGS_TX_CHK_SHIFT     BIT(1)
#define DESC_FLAGS_TX_LAST     BIT(2)
#define DESC_FLAGS_TX_OWN     BIT(3)
#define DESC_FLAGS_TX_CPC_CRC_PAD_INSER   BIT(4)
#define DESC_FLAGS_TX_CPC_CRC_INSER         BIT(5)
#define DESC_FLAGS_TX_CPC_PAD_INSER     BIT(6)
#define DESC_FLAGS_TX_CPC_CRC_REPLA     BIT(7)
#define DESC_FLAGS_TX_SAIC_REPLA     BIT(8)
#define DESC_FLAGS_IC               BIT(9)
#define DESC_FLAGS_TIMESTAMP        BIT(10)

enum rx_frame_status dwmac_wrback_get_rx_status(struct dma_desc *d);

enum tx_frame_status dwmac_wrback_get_tx_status(struct dma_desc *d);

void dwmac_set_rx_owner(struct dma_desc *p, uint32 disable_rx_ic);

uint16 dwmac_wrback_get_rx_frame_len(struct dma_desc *p);

sint32 dwmac_wrback_get_tx_timestamp_status(struct dma_desc *p);

uint32 dwmac_wrback_get_rx_timestamp_status(struct dma_desc *desc, struct dma_desc *next_desc);

void dwmac_rd_init_rx_desc(struct dma_desc *p, uint32 disable_rx_ic);

void dwmac_rd_init_tx_desc(struct dma_desc *p);

void dwmac_rd_prepare_tx_desc(struct dma_desc *p, uint32 len, \
                              uint32 tot_pkt_len, uint32 flags);
void dwmac_set_addr(struct dma_desc *p, uint32 *addr);

void dwmac_clear(struct dma_desc *p);

#ifdef __cplusplus
}
#endif

#endif

